This invention is in the field of digital computers. In particular, it relates to battery powered portable computers and their memory subsystems.
One of the fastest growing areas in the computer industry is portable computers. Portable computers have grown both much lighter and much more capable over the past few years. One factor, however, which still limits their usefulness is the comparatively short length of time that such computers can operate using their internal battery power supply before requiring a recharge. Although research on new batteries promises batteries of much greater power density and consequently longer operating times, it is uncertain when these batteries will become available. Even when better batteries become available, the power they can supply will always remain a limiting resource, necessitating its conservation.
Given the uncertainty about the availability of new power sources, engineers designing portable computers have concentrated on reducing the power consumed by their computers, thereby extending battery life. Examples of such efforts include the many different types of "sleep" modes which have been incorporated into portable computers, which modes either turn off the computer's central processing unit ("CPU") when the computer is idle or reduce the computer's clock frequency during such idle periods, thereby also reducing power usage. Many other examples of power reduction efforts could be given.
One area that has so far remained resistant to such power use reduction efforts is the dynamic random access memory ("DRAM") array and the write-enable and multiplexed address lines that couple the DRAM array to the DRAM controller and the CPU. The address lines that couple these devices together are, as a general rule, relatively long, especially when compared to the signal path lengths within the devices. Also, as there are many individual DRAM devices in a DRAM array, the length and number of address lines is even greater. The capacitive load seen by the integrated circuit ("IC") driving a write enable or address line to the DRAM array is the trace capacitance of the line on the printed circuit ("PC") board, plus the sum of the input capacitances of the individual DRAM devices connected to that line, a sum that can be relatively large in the case of a large DRAM array. Each transition on a DRAM address or write enable line requires either charging or discharging the total capacitive load on that line. The power requirements of these charging/discharging operations are calculated using the following formula: EQU Power=Capacitance*Frequency*Voltage.sup.2.
For a typical system, each DRAM access requires three DRAM address line transitions. With a system clock frequency of 25 MHz and each access requiring 5 clock cycles, the maximum rate of access is 5 MHz. Therefore, up to 15 million DRAM address line transitions can occur each second. With a voltage change of +/-5 volts and a line capacitance of about 300 picofarad, the amount of power used on a single line can equal up to 56 milliwatts. Given that there are currently 12 address lines to a typical multiplexed DRAM array, this quickly amounts to a significant amount of power. It should be noted that the number of address lines used in a DRAM array has increased with each new generation of DRAM memory.
Known computer systems allow the DRAM array's address and control lines to mirror every change which occurs on the CPU's address and read/write lines, even if these changes indicate accesses to devices other than the DRAM array. This practice causes many unnecessary, power wasting transitions on the DRAM control and address lines, especially considering the fact that only 25-35% of all system operations involve the DRAM array. In addition, the multiplexer which switches the DRAM address lines from the row to the column portion of the CPU address typically switches back to the row portion of the address at the end of each DRAM access cycle, which is yet another unnecessary transition on the DRAM address lines. The waste of power that these unnecessary DRAM address line transitions represents will only become worse in new computer systems as both the clock frequency and the number of DRAM address lines of such systems continues to increase.
Although engineers have been aware of the power wasting nature of these unnecessary DRAM address line transitions, attempts to reduce them have not been successful. One problem has been that most engineers assumed that a great deal of extra circuit logic would have to be used to eliminate the unnecessary transitions. Unfortunately, such logic would introduce timing delays in generating the needed control signals. Such timing delays would not be acceptable in an optimized DRAM controller. The inventors are not aware of any other proposed solution to this problem which will not have a negative impact on system performance.